This invention relates to semiconductor memory devices and more particularly to MOS read-only type memories of the electrically programmable type.
Floating gate type electrically programmable read-only memory or EPROM devices are usually manufactured using cell layouts as seen in U.S. Pat. No. 4,112,509 and 4,112,544, issued to Wall and McElroy, assigned to Texas Instruments, or in U.S. Pat. No. 3,984,822. Several manufacturers produce EPROM devices of layout such as this in 8K, 16K, 32K and more recently 64K bit sizes. The continuing demand for higher speed and lower cost, however, requires reduction in cell size or increase in bit density while at the same time maintaining process compatability with existing double-level polysilicon N-channel manufacture. One of the classic techniques for increasing the array density in read-only type memories is the use of a virtual ground configuration instead of providing a ground line for each column or output line. Virtual ground memories are disclosed in U.S. Pat. No. 3,934,233 issued to Fisher and Rogers or U.S. Pat. No. 4,021,781 issued to E. R. Caudel, both assigned to Texas Instruments. A virtual ground EPROM layout is shown in U.S. Pat. No. 4,151,021, issued to David J. McElroy, assigned to Texas Instruments. The high voltage transients and high currents required in programming of floating gate EPROMs place more stringent demands on the decode circuitry than on the circuits previously employed in virtual ground devices. For this reason, prior EPROM layouts used separate contacts and lines to each cell, which unfortunately required excess space on the chip. However, when separate ground select and column select functions are used, as needed for operation of a virtual ground memory, the column decode employed is of different complexity compared to dedicated ground type memory devices. This column and ground select addressing, as well as row addressing for large, high speed devices, imposes new requirements on decode circuitry. The demand by customers for low power operation of EPROM devices has necessitated implementation of a power-down mode different from the usual standby mode of operation. In the power-down mode the EPROM device will not respond to an address, yet when exiting from power-down there must not be an unduly long period before normal access is permitted. It is within these constraints and often conflicting requirements that improved EPROMs are being designed.
It is the principal object of this invention to provide an improved electrically programmable read only memory device, particularly one which is of smaller size or greater bit density. Another object is to provide an improved electrically programmable memory device which is of low power dissipation or is capable of power-down operation. A further object is to provide an arrangement for accessing a memory array for read and/or programming in an improved manner.